GD25VE32CSMS datasheet(18/63 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VE32C

in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect

(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is

not executed once the Hardware Protected Mode is entered.

Figure 6. Write Status Register Sequence Diagram

7.6. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the

rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max

frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read

with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 7. Read Data Bytes Sequence Diagram

Command

01H/31H/11H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

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