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CS5340 数据表(PDF) 13 Page - Cirrus Logic |
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CS5340 数据表(HTML) 13 Page - Cirrus Logic |
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13 / 24 page ![]() CS5340 DS601PP2 13 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) * For a description of Speed Modes, please refer to Table 1 on page 17. Parameter Symbol Min Typ Max Unit MCLK Specifications MCLK Period tclkw 36 - 45 ns 72 - 1953 ns MCLK Pulse Width High tclkh 15 - - ns MCLK Pulse Width Low tclkl 15 - - ns Master Mode SCLK falling to LRCK tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo 0- 32 ns SCLK Duty Cycle - 50 - % Slave Mode Single Speed* LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 145 - - ns SCLK Low tsclkl 55 - - ns SCLK falling to SDOUT valid tdss -- 32 ns SCLK falling to LRCK edge tslrd -20 - 20 ns Double Speed* LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 145 - - ns SCLK Low tsclkl 55 - - ns SCLK falling to SDOUT valid tdss -- 32 ns SCLK falling to LRCK edge tslrd -20 - 20 ns Quad Speed* LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 78 - - ns SCLK Low tsclkl 40 - - ns SCLK falling to SDOUT valid tdss -- 32 ns SCLK falling to LRCK edge tslrd -8 - 8 ns |
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