CS5340

DS601PP2

3

LIST OF FIGURES

Figure 1. Single Speed Mode Stopband Rejection ....................................................................... 10

Figure 2. Single Speed Mode Stopband Rejection ....................................................................... 10

Figure 3. Single Speed Mode Transition Band (Detail)................................................................. 10

Figure 4. Single Speed Mode Passband Ripple ........................................................................... 10

Figure 5. Double Speed Mode Stopband Rejection...................................................................... 10

Figure 6. Double Speed Mode Stopband Rejection...................................................................... 10

Figure 7. Double Speed Mode Transition Band (Detail) ............................................................... 11

Figure 8. Double Speed Mode Passband Ripple .......................................................................... 11

Figure 9. Quad Speed Mode Stopband Rejection ........................................................................ 11

Figure 10. Quad Speed Mode Stopband Rejection ...................................................................... 11

Figure 11. Quad Speed Mode Transition Band (Detail) ................................................................ 11

Figure 12. Quad Speed Mode Passband Ripple........................................................................... 11

Figure 13. Master Mode, Left Justified SAI ................................................................................... 14

Figure 14. Slave Mode, Left Justified SAI ..................................................................................... 14

Figure 15. Master Mode, I2S SAI .................................................................................................. 14

Figure 17. Typical Connection Diagram ........................................................................................ 16

Figure 18. CS5340 Master Mode Clocking ................................................................................... 18

Figure 19. Left-Justified Serial Audio Interface ............................................................................. 19

Figure 20. I2S Serial Audio Interface............................................................................................. 19

Figure 21. CS5340 Recommended Analog Input Buffer............................................................... 20

Figure 22. CS5340 THD+N versus Frequency ............................................................................. 21

LIST OF TABLES

Table 1. Speed Modes and the Associated Output Sample Rates (Fs)........................................ 17

Table 2. CS5340 Mode Control..................................................................................................... 17

Table 3. Master Clock (MCLK) Ratios........................................................................................... 19

Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates .......................... 19

Table 5. Revision History .............................................................................................................. 24