CS5340

DS601PP2

21

4.7

Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure

synchronous sampling, the MCLK and LRCK must be the same for all of the CS5340’s in the system. If only one

master clock source is needed, one solution is to place one CS5340 in Master mode, and slave all of the other

CS5340’s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all

clocks from the same external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will

ensure that all converters begin sampling on the same clock edge.

4.8

Capacitor Size on the Reference Pin (FILT+)

The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decou-

pling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor val-

ues used to optimize low frequency distortion performance.

Figure 22. CS5340 THD+N versus Frequency

47 uF

100 uF

22 uF

10 uF

6.8 uF

4.7 uF

3.3 uF

2.2 uF

1 uF

5.6 uF