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C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 13 of 25
Approved Product
Group Timing Relationship and Tolerances
Offset
Tolerance
Conditions
3V66 to PCI
2.5 nS
±1.0 nS
3V66 Leads PCI (un-buffered mode)
USB to DOT 48M Skew
0.0 nS
±1.0 nS
0 degrees phase shift
66B(0:2) to PCI offset
2.5 nS
±1.0 nS
66B leads PCI (buffered mode)
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for VCH (48MHz) operation it is also in phase with the USB
and DOT outputs.
USB48M
DOT48M
48MUSB and 48MDOT Phase Relationship Figure
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown below.
66IN
66CB0:2)
Tpd
66IN to 66B(0:2) Output Delay Figure
The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The measurement taken at 1.5 volts.
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