21 / 25 page

C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 21 of 25
Approved Product
VTT_PWRGD# Timing Diagram
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_GD#
Sample Sels
Off
Off
On
On
State 1
(Note A)
Note A: Device is not effected, VTT_PWRGD# is ignored.
Clock Generator PowerUp/Run State Diagram
Delay 0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs (pins
54,55)
S2
VDD3.3 = Off
Normal
Operation
S3
Enable Outputs