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ADL8111ACCZN-R7 数据表(PDF) 3 Page - Analog Devices |
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ADL8111ACCZN-R7 数据表(HTML) 3 Page - Analog Devices |
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3 / 24 page  Data Sheet ADL8111 Rev. 0 | Page 3 of 24 SPECIFICATIONS Drain bias voltage (VDD_PA) = +5 V, quiescent drain supply current (IDQ_PA) = 70 mA, negative bias voltage (VSS_SW) = −3.3 V, positive bias voltage (VDD_SW) = +3.3 V, and TA = 25°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTION Frequency Range 10 5000 MHz INTERNAL AMPLIFIER STATE Small Signal Gain 11.2 12.5 dB Gain Flatness ±0.5 dB Input Return Loss 24 dB Output Return Loss 17 dB Radio Frequency (RF) Settling Time 50% VA/VB to 0.5 dB margin of final RFOUT 170 ns 50% VA/VB to 0.1 dB margin of final RFOUT 260 ns Switching Speed Rise Time (tRISE) and Fall Time (tFALL) 10% to 90% RFOUT 40 ns Turn On Time (tON) and Turn Off Time (tOFF) 50% VA/VB to 90%/10% RF 160 ns Output 1 dB Compression (P1dB) 17 19.5 dBm Output Third-Order Intercept (OIP3) 34 dBm Noise Figure 2.8 dB VDD_PA 3.0 5.0 5.5 V INTERNAL BYPASS SWITCH STATE Insertion Loss 2 dB RF Settling Time 50% VA/VB to 0.5 dB margin of final RFOUT 175 ns 50% VA/VB to 0.1 dB margin of final RFOUT 260 ns Switching Speed tRISE/tFALL 10% to 90% RFOUT 60 ns tON/tOFF 50% VA/VB to 90%/10% RF 160 ns Input Third-Order Intercept (IIP3) 58 dBm 0.5 dB Compression (P0.5dB) 34 dBm P1dB 35 dBm Return Loss On State 18 dB Return Loss Off State 30 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES Insertion Loss 1 dB RF Settling Time 50% VA/VB to 0.5 dB margin of final RFOUT 180 ns 50% VA/VB to 0.1 dB margin of final RFOUT 230 ns Switching Speed tRISE/tFALL 10% to 90% RFOUT 70 ns tON/tOFF 50% VA/VB to 90%/10% RF 175 ns IIP3 59 dBm P0.5dB 35.5 dBm P1dB 36 dBm Return Loss On State 22 dB Return Loss Off State 25 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V |
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