Data Sheet

ADL8111

Rev. 0 | Page 21 of 24

APPLICATIONS INFORMATION

The basic connections for operating the ADL8111 are shown in

Figure 83. A 5 V dc bias is supplied to the amplifier on VDD_PA,

+3.3 V dc bias supply to VDD_SW and −3.3 V dc bias supply to

VSS_SW.

VA and VB are digital inputs set path states shown in Table 7.

High logic state is set at 1.4 V and low logic state is set at 0 V.

The LNA within the ADL8111 operates in self-biased mode

where the VBIAS pin is connected to a 560 Ω external resistor

to achieve a 70 mA supply current. Refer to Table 9 for the

RECOMMENDED BIAS SEQUENCING

During Power-Up

The recommended bias sequence during power-up follows:

1. Set VDD_SW = 3.3 V.

2. Set VSS_SW = −3.3 V.

3. Set VDD_PA = 5 V.

4. Apply the RF signal.

During Power-Down

The recommended bias sequence during power-down follows:

1. Turn off the RF signal.

2. Set VDD_PA = 0 V.

3. Set VSS_SW = 0 V.

4. Set VDD_SW = 0 V.

recommended operating point to achieve optimum

performance. The data used in this data sheet was taken with

the recommended bias condition. Using the HMC8411 with

different bias conditions can provide different performance

than what is shown in the Typical Performance Characteristics

section.

Table 9. Recommended Bias Resistor Values at VDD_PA = 5 V

226

85

560

70

1.1 k

55