TMS320DM643 datasheet(63/160 Pages) TI

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4.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Case Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS (1)

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

DVDD = MIN, IOH = MAX

2.4

VOL

Low-level output voltage

DVDD = MIN, IOL = MAX

0.4

VI = VSS to DVDD no opposing internal

±10

resistor

VI = VSS to DVDD opposing internal pullup

Input current

100

150

resistor (2)

VI = VSS to DVDD opposing internal

–150

–100

–50

pulldown resistor (2)

EMIF, CLKOUT4, CLKOUT6, EMUx

–16

Video Ports, Timer, TDO, GPIO

IOH

High-level output current

–8

(Excluding GP0[2:1]), McBSP

HPI

–0.5

EMIF, CLKOUT4, CLKOUT6, EMUx

Video Ports, Timer, TDO, GPIO

(Excluding GP0[2:1]), McBSP

IOL

Low-level output current

SCL0 and SDA0

HPI

1.5

IOZ

Off-state output current

VO = DVDD or 0 V

±10

CVDD = 1.4 V, CPU clock = 600 MHz

890

ICDD

Core supply current(3)

CVDD = 1.2 V, CPU clock = 500 MHz

620

DVDD = 3.3 V, CPU clock = 600 MHz

210

IDDD

I/O supply current(3)

DVDD = 3.3 V, CPU clock = 500 MHz

165

Input capacitance

Output capacitance

(1)

For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2)

Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(3)

Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz

EMIF for -500 speed). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder

performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

•

High-DSP-Activity Model:

–

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

–

McBSP: 1 channel at 2.048 MHz

–

Timers: 2 timers at maximum rate

•

Low-DSP-Activity Model:

–

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

–

McBSP: 1 channel at 2.048 MHz

–

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power

Consumption Summary application report (literature number SPRA962).

Device Operating Conditions

TMS320DM643 数据表(PDF) 63 Page - Texas Instruments

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