11-272
RF2958
Rev A0 050209
GENERAL APPLICATION INFORMATION
This part is used at high frequencies. Proper attention to layout and component selection is critical in order to achieve the
specified performance. Values for DC blocking capacitors and power supply bypass capacitors should be selected so
that they are series self-resonant at the frequency of operation. In addition, transmission line techniques should always
be used on signal lines at RF frequencies, and may be required on signal lines at IF frequencies if connections are long
with respect to wavelength.
The RF2958 should be powered from regulated supply. If not sharing this supply with the MCLK oscillator, the MCLK
oscillator should also be powered from a well-regulated supply. Avoid sharing the RF2958 and MCLK oscillator supplies
with the baseband processor and/or MAC.
Power supply bypassing of VCC lines for the PLL is critical in order to minimize the effects of power supply noise on
phase noise performance. In addition to RF/IF bypassing, these lines should be bypassed with low-frequency capacitors.
A value of 0.01
µF is sufficient for most applications, but performance should be verified by looking at a modulated signal
on a vector signal analyzer or a constant signal on a spectrum analyzer or phase noise test set.
Since this is a mixed-signal device, care should be taken to separate traces connecting to digital circuits from those con-
necting to analog circuits. Power supply bypassing is important to keep the noise contributions of digital circuits to a min-
imum. It is generally better to start with more bypassing than you think you need, then remove components and re-
evaluate performance.
ENABLE/DISABLE MODES
Operation of the device is controlled by the MODE0 and MODE1 pins according to the following truth table.
When switching between modes, ensure that MODE0 and MODE1 are high for less than three master clock cycles to
avoid inadvertently entering reset modes. To enter reset mode, ensure that MODE0 and MODE1 are high for at least five
master clock cycles.
In Idle mode, the IF and RF PLLs are locked and the baseband circuitry is powered; everything else is disabled. In Reset
mode, the voltage regulators for the digital circuitry inside the part are enabled; everything else is disabled.
Additionally, there is a hibernate mode in which everything is disabled. This mode is entered by writing the value 8h to
Register 0 while in hibernate mode. The MODE0 and MODE1 pins should be held high while in hibernate mode. To exit
this mode, toggle the states of one or both MODE pins. All registers will need to be reprogrammed on exiting hibernate
mode.
RECEIVER
Front End LNA/Mixer
The LNA/Mixer provides 35dB conversion gain to IF in high-gain mode to detect weak signals at the antenna. In low-gain
mode, the LNA/Mixer provides 2dB conversion gain. The LNA GS pin selects gain mode. When LNA GS is high, the part
is in high-gain mode. The mixer output is connected to the IF OUT pins as a differential signal for connecting to an exter-
nal SAW filter. Proper matching at the input and output of the SAW filter is essential for maintaining performance through
the system. The IF input and output differential impedances are 750
Ω nominal.
The same filter is used for transmitter and receiver. Internal switches control which signal is present at the SAW filter. If
AC-coupling is required for the SAW filter, use values less than 150pF to ensure that switching speed will not be seri-
ously degraded.
MODE0
MODE1
Function
00
Idle
0
1
Transmit Enable
1
0
Receive Enable
11
Reset
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