CS61318

DS441PP2

21

LLOOP - Local Loopback Input, Pin 27(Hardware Mode).

Setting LLOOP to a logic 1 internally routes the transmitter input to the receiver output. If TAOS is low,

the signal being output from the transmitter will be internally routed to the receiver inputs allowing nearly

the entire chip to be tested. If TAOS and LLOOP are set high at the same time, the local loopback will

occur at the jitter attenuator (excluding the transmit and receive circuitry) and the transmitter will

transmit all ones. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the

CS61318. Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.

RLOOP - Remote Loopback Input, Pin 26 (Hardware Mode).

Setting RLOOP to a logic 1 causes the received signal to be passed through the jitter attenuator (if

active) and retransmitted onto the line. The internal encoders/decoders will be bypassed in Remote

Loopback. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the CS61318.

Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.

JASEL - Jitter Attenuator Select, Pin 11.

If the jitter attenuator is enabled (crystal oscillator active, or XTALIN tied low or floated with MCLK

provided), setting JASEL high places the jitter attenuator in the receive path; setting JASEL low places

the jitter attenuator in the transmit path.

NC - No Connect, Pin 17.

The input voltage to this pin does not effect normal operation.

4.4

Status

LOS - Loss Of Signal Output, Pin 12.

LOS goes high when 175 consecutive zeros are received. LOS returns low when the ones density

reaches 12.5% (based on 175 consecutive bit periods, starting with a one and containing less than 100

consecutive zeros, as prescribed in ITU-T G.775). If LOS is true, and the jitter attenuator is in the

receive path, RCLK will smoothly transition to MCLK if provided; RCLK will retain the frequency prior to

LOS if MCLK is grounded. If the jitter attenuator is NOT in the receive path, RCLK will become the

reference clock frequency (MCLK) if provided, or the crystal oscillator.

NLOOP - Network Loopback Output, Pin 23 (Hardware Mode).

NLOOP goes high when a 00001 pattern is received for five seconds putting the CS61318 into network

(remote) loopback. NLOOP is deactivated upon receipt of a 001 pattern for five seconds, or by selection

of LLOOP or RLOOP.

LATN - Line Attenuation Indication Output, Pin 18.

LATN is an encoded output that indicates the receive equalizer gain setting in relation to a five RCLK

cycle period. If LATN is high for one RCLK cycle, the equalizer is set for 9.5 dB gain, two cycles =

19.5 dB gain, three cycles = 28.5 dB gain, four cycles = 0 dB. LATN may be sampled on the rising edge

of RCLK.

4.5

Serial Control Interface

INT - Interrupt Output, Pin 23 (Host Mode).

INT pulls low to flag the host processor when NLOOP, AIS or LOS changes state. INT is an open drain

output and should be tied to the supply through a resistor.