| 数据搜索系统,热门电子元器件搜索 |
|
V62/12615-01XE-R 数据表(PDF) 30 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
V62/12615-01XE-R 数据表(HTML) 30 Page - Texas Instruments |
|
30 / 98 page ![]() CRS_DV X1 RXD[1:0] RX_ER T2.27.2 T2.27.1 T2.27.2 PMD Input Pair T2.27.3 T2.27.5 RX_DV T2.27.2 T2.27.2 IDLE (J/K) Data (TR) Data T2.27.4 30 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated (1) Per the RMII Specification, output delays assume a 25-pF load. (2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion. (3) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data. 4.7.27 RMII Receive Timing PARAMETER DESCRIPTION NOTES(1) (2) (3) MIN TYP MAX UNIT T2.27.1 X1 clock period 50-MHz reference clock 20 ns T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising 2 14 ns T2.27.3 CRS ON delay From JK symbol on PMD receive pair to initial assertion of CRS_DV 18.5 bits T2.27.4 CRS OFF delay From TR symbol on PMD receive pair to initial deassertion of CRS_DV 27 bits T2.27.5 RXD[1:0] and RX_ER latency From symbol on receive pair. Elasticity buffer set to default value (01). 38 bits Figure 4-28. RMII Receive Timing |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |