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V62/12615-01XE-R 数据表(PDF) 4 Page - Texas Instruments |
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V62/12615-01XE-R 数据表(HTML) 4 Page - Texas Instruments |
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4 / 98 page ![]() 4 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DP83848-EP Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated 3 Pin Configuration and Functions The DP83848-EP pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial management interface • MAC data interface • Clock interface • LED interface • Reset • Strap options • 10/100 Mbps PMD interface • Special connect pins • Power and ground pins All DP83848-EP signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. NOTE Strapping pin option. See Table 3-8 for strap definitions. Type: I Input Type: O Output Type: I/O Input/Output Type: OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-k Ω resistor should be used. See Table 3-8 for details.) |
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