gram cycle. This STOP condition will trigger an

internal memory program cycle only if the STOP

condition is internally decoded right after the ACK

bit; any STOP condition decoded out of this ”10th

bit” time slot will not trigger the internal program-

ming cycle. All inputs are disabled until the comple-

tion of this cycle and the ST24/25E64 will not

respond to any request.

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the ST24/25E64

disable itself from the bus in order to copy the data

from the internal latches to the memory cells. The

AC Characteristics table, this timing value may be

reduced by an ACK polling sequence issued by the

master.

The sequence is:

– Initial condition: a Write is in progress (see Fig-

ure 7).

– Step 1: the Master issues a START condition

followed by a Device Select byte. (1st byte of

the new instruction)

– Step 2: if the ST24/25E64 are internally writ-

ing, no ACK will be returned. The Master goes

back to Step1. If the ST24/25E64 have termi-

nated the internal writing, it will issue an ACK.

The ST24/25E64 are ready to receive the sec-

ond part of the instruction (the first byte of this

instruction was already sent during Step1).

WRITE Cycle

in Progress

AI01099B

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YES

NO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by ST24xxx

Figure 7. Write Cycle Polling using ACK

9/16

ST24E64, ST25E64