AI01204B

3

E0-E2

SDA

VCC

ST24E64

ST25E64

WC

SCL

VSS

Figure 1. Logic Diagram

E0 - E2

Chip Enable Inputs

SDA

Serial Data Address Input/Output

SCL

Serial Clock

WC

Write Control

Supply Voltage

Ground

Table 1. Signal Names

ST24E64

ST25E64

SERIAL EXTENDED ADDRESSING COMPATIBLE

PRELIMINARY DATA

November 1996

1/16

This is preliminary information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.

ADDRESSING

TWO WIRE SERIAL INTERFACE,

SUPPORTS 400kHz PROTOCOL

1 MILLION ERASE/WRITE CYCLES, OVER

the FULL SUPPLY VOLTAGE RANGE

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE

– 4.5V to 5.5V for ST24E64 version

– 2.5V to 5.5V for ST25E64 version

WRITE CONTROL FEATURE

BYTE and PAGE WRITE (up to 32 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

DESCRIPTION

The ST24/25E64 are 64K bit electrically erasable

programmable memories (EEPROM), organized

as 8 blocks of 1024 x 8 bits. The ST25E64 operates

with a power supply value as low as 2.5V. Both

Plastic Dual-in-Line and Plastic Small Outline pack-

ages are available.

8

1

SO8 (M)

200mil Width

8

1

PSDIP8 (B)

0.25mm Frame