56F8167 datasheet(116/184 Pages) FREESCALE

116 / 184 page

56F8367 Technical Data, Rev. 7.0

116

Freescale Semiconductor

Preliminary

6.5.2.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.2.2

Software Reset (SWR)—Bit 5

When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST

bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing

a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.

6.5.2.3

COP Reset (COPR)—Bit 4

When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has

occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will

set the bit, while writing a 1 to the bit will clear it.

6.5.2.4

External Reset (EXTR)—Bit 3

If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On

Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position

will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external

RESET pin being asserted low.

6.5.2.5

Power-On Reset (POR)—Bit 2

When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can only be

cleared by software or by another type of reset. Writing a 0 to this bit will set the bit while writing a 1 to

the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a

Power-On Reset.

6.5.2.6

Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.3

SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,

and SIM_SCR3)

Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.

Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)

6.5.3.1

Software Control Data 1 (FIELD)—Bits 15–0

This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is

intended for use by a software developer to contain data that will be unaffected by the other reset sources

(RESET pin, software reset, and COP reset).

Base + $2

Read

FIELD

Write

POR

000

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