56F8167 datasheet(119/184 Pages) FREESCALE

119 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

119

Preliminary

The upper four bits of the GPIOB register can function as GPIO, [A23:20], or as additional clock output

signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed

to operate as peripheral outputs, then the choice between [A23:20] and additional clock outputs is done

here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as

[A23:20]. This can be changed by altering [A23:20] as shown in Figure 6-9.

Figure 6-9 CLKO Select Register (SIM_CLKOSR)

6.5.7.1

Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.7.2

Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9

•

0 = Peripheral output function of GPIOB7 is defined to be A23

•

1 = Peripheral output function of GPIOB7 is defined to be the oscillator_clock (MSTR_OSC in Figure 3-4)

6.5.7.3

Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8

•

0 = Peripheral output function of GPIOB6 is defined to be A22

•

1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2

6.5.7.4

Alternate GPIOB Peripheral Function for A21 (A21)—Bit 7

•

0 = Peripheral output function of GPIOB5 is defined to be A21

•

1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK

6.5.7.5

Alternate GPIOB Peripheral Function fpr A20 (A20)—Bit 6

•

0 = Peripheral output function of GPIOB4 is defined to be A20

•

1 = Peripheral output function of GPIOB4 is defined to be the prescaler_clock (FREF in Figure 3-4)

6.5.7.6

Clockout Disable (CLKDIS)—Bit 5

•

0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL

•

1 = CLKOUT is tri-stated

6.5.7.7

CLockout Select (CLKOSEL)—Bits 4–0

Selects clock to be muxed out on the CLKO pin.

•

00000 = SYS_CLK (from OCCS - DEFAULT)

•

00001 = Reserved for factory test—56800E clock

•

00010 = Reserved for factory test—XRAM clock

•

00011 = Reserved for factory test—PFLASH odd clock

Base + $A

Read

A23

A22

A21

A20

CLK

DIS

CLKOSEL

Write

RESET

001

000

56F8167 数据表(PDF) 119 Page - Freescale Semiconductor, Inc

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