56F8167 datasheet(123/184 Pages) FREESCALE

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56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

123

Preliminary

6.5.8.2

GPIOD1 (D1)—Bit 5

This bit selects the alternate function for GPIOD1.

•0 = CS3

•1 = CAN2_RX

6.5.8.3

GPIOD0 (D0)—Bit 4

•0 = CS2

•1 = CAN2_TX

6.5.8.4

GPIOC3 (C3)—Bit 3

This bit selects the alternate function for GPIOC3.

•

0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the

56F8300 Peripheral User Manual)

•

1 = SS1

6.5.8.5

GPIOC2 (C2)—Bit 2

This bit selects the alternate function for GPIOC2.

•

0 = INDEX1/TB2 (default)

•1 = MISO1

6.5.8.6

GPIOC1 (C1)—Bit 1

This bit selects the alternate function for GPIOC1.

•

0 = PHASEB1/TB1 (default)

•1 = MOSI1

6.5.8.7

GPIOC0 (C0)—Bit 0

This bit selects the alternate function for GPIOC0.

•

0 = PHASEA1/TB0 (default)

•

1 = SCLK1

6.5.9

Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings

feature. The clocks can be individually controlled for each peripheral on the chip.

Figure 6-13 Peripheral Clock Enable Register (SIM_PCE)

Base + $C

Read

EMI

ADCB ADCA

CAN

DEC1

DEC0

TMRD

TMRC

TMRB

TMRA

SCI 1

SCI 0

SPI 1

SPI 0

PWMB

PWMA

Write

RESET

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