56F8167 datasheet(126/184 Pages) FREESCALE

126 / 184 page

56F8367 Technical Data, Rev. 7.0

126

Freescale Semiconductor

Preliminary

6.5.10

I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)

The I/O Short Address Location registers are used to specify the memory referenced via the I/O short

address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;

the upper address bits are not directly controllable. This register set allows limited control of the full

address, as shown in Figure 6-14.

Note:

If this register is set to something other than the top of memory (EOnCE register space) and the EX bit

in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions

will be affected.

Figure 6-14 I/O Short Address Determination

With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral

registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register

to its previous contents prior to returning from interrupt.

Note:

The default value of this register set points to the EOnCE registers.

Note:

The pipeline delay between setting this register set and using short I/O addressing with the new value

is three cycles.

Figure 6-15 I/O Short Address Location High Register (SIM_ISALH)

6.5.10.1

Input/Output Short Address Low (ISAL[23:22])—Bit 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

Base + $D

Read

ISAL[23:22]

Write

RESET

11111

Instruction Portion

“Hard Coded” Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_ISALL Register

2 bits from SIM_ISALH Register

Full 24-Bit for Short I/O Address

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