56F8167 datasheet(128/184 Pages) FREESCALE

128 / 184 page

56F8367 Technical Data, Rev. 7.0

128

Freescale Semiconductor

Preliminary

6.7 Power Down Modes Overview

The 56F8367/56F8167 operate in one of three power-down modes as shown in Table 6-3

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as

the main processor frequency in this architecture. The maximum frequency of operation is

SYS_CLK = 60MHz.

Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system

frequency which can be controlled through the OCCS.

6.8 Stop and Wait Mode Disable Function

Figure 6-17 Stop Disable Circuit

Table 6-4 Clock Operation in Power Down Modes

Mode

Core Clocks

Peripheral Clocks

Description

Run

Active

Device is fully functional

Wait

Core and memory

clocks disabled

Active

Peripherals are active and can produce interrupts if they

have not been masked off.

Interrupts will cause the core to come out of its

suspended state and resume normal operation.

Typically used for power-conscious applications.

Stop

System clocks continue to be generated in

the SIM, but most are gated prior to

reaching memory, core and peripherals.

The only possible recoveries from Stop mode are:

1. CAN traffic (1st message will be lost)

2. Non-clocked interrupts

3. COP reset

4. External reset

5. Power-on reset

D-FLOP

56800E

STOP_DIS

Permanent

Disable

Reprogrammable

Disable

Clock

Select

Reset

Note: Wait disable circuit is similar

56F8167 数据表(PDF) 128 Page - Freescale Semiconductor, Inc

56F8167 数据表(HTML) 128 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载