56F8167 datasheet(131/184 Pages) FREESCALE

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Flash Access Blocking Mechanisms

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

131

Preliminary

The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to

control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control

the period of the clock used for timed events in the FM erase algorithm. This register must be set with

appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300

Peripheral User Manual for more details on setting this register value.

The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides

down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the

PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV

must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD

equations for calculating the correct values.

Figure 7-1 JTAG to FM Connection for Lockout Recovery

Two examples of FM_CLKDIV calculations follow.

EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up,

the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation

yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This

translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.

SYS_CLK

JTAG

FMCLKD

DIVIDER

FM_CLKDIV

FM_ERASE

Flash Memory

clock

input

SYS_CLK

(2)

)

(

(DIV + 1)

150[kHz]

200[kHz]

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