CY8CKIT-059 datasheet(24/48 Pages) CYPRESS

24 / 48 page

CY8CKIT-059 PSoC® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G

Hardware

4.2.4

Board Separation (Snapping)

The PSoC 5LP Prototyping Kit consists of both a PSoC 5LP and a KitProg board. To separate the

two boards for testing or development, break the two boards apart at the built-in perforated edge.

The easiest method of separating the two boards is to place the kit on the edge of a table, where the

edge of the table is directly below the perforated edge and the smaller KitProg board is off the table

edge. Press gently on the KitProg board and snap the two boards apart. If any material is removed

from the edge of the boards, use sheers to clean up the edge of the kit.

Figure 4-4. PSoC 5LP Prototyping Kit Broken into Two Parts

4.2.5

Header Connections

The PSoC 5LP Prototyping Kit supports a number of unpopulated headers on both the KitProg and

the target PSoC 5LP boards.

4.2.5.1

Functionality of the J1 and J2 Headers (Target Board)

The target board contains two dual-inline headers (J1 and J2). These headers are both 1×26-pin

headers and include all of the I/O available on the PSoC 5LP device. These headers support all of

the available ports, GND, VDD, and connections to passive elements and user-input devices.

The J1 and J2 headers support 100-mil spacing, so you can solder connectors to connect the target

board to any development breadboard.

Figure 4-5. J1 and J2 Headers

CY8CKIT-059 数据表(PDF) 24 Page - Cypress Semiconductor