HPC-DEV-IBMC datasheet(16/30 Pages) NSC

16 / 30 page

MICROWIREPLUS Operation

The HPC46400E can enter the MICROWIREPLUS mode

as the master or a slave A control bit in the IRCD register

determines whether the HPC46400E is the master or slave

The shift clock is generated when the HPC46400E is config-

ured as a master An externally generated shift clock on the

SK pin is used when the HPC46400E is configured as a

slave When the HPC46400E is a master the DIVBY regis-

ter programs the frequency of the SK clock The DIVBY

14 selectable steps from 122 Hz to 1 MHz with CKI at

16 MHz

The contents of the SIO register may be accessed through

any of the memory access instructions Data waiting to be

transmitted in the SIO register is shifted out on the falling

edge of the SK clock Serial data on the SI pin is latched in

on the rising edge of the SK clock

HPC46400E UART

The HPC46400E contains a software programmable UART

The UART (see

Figure 16 ) consists of a transmit shift regis-

ter a receiver shift register and five addressable registers

as follows a transmit buffer register (TBUF) a receiver buff-

er register (RBUF) a UART control and status register

(ENU) a UART receive control and status register (ENUR)

and a UART interrupt and clock source register (ENUI) The

ENU register contains flags for transmit and receive func-

tions this register also determines the length of the data

frame (7 8 or 9 bits) and the value of the ninth bit in trans-

mission The ENUR register flags framing parity and data

overrun errors while the UART is receiving Other functions

of the ENUR register include saving the ninth bit received in

the data frame reporting receiving and transmitting status

and enabling or disabling the UART’s Wake-up Mode of op-

eration The determination of an internal or external clock

source is done by the ENUI register as well as selecting the

number of stop bits (

1 1

2) selecting between the

synchronous or asynchronous mode and enabling or dis-

abling transmit and receive interrupts

The clock inputs to the Transmitter and Receiver sections

of the UART can be individually selected to come from ei-

ther an off-chip source on the CKX pin or one of the three

on-chip sources Presently two of the on-chip sources the

Divide-By (DIVBY) Register and the Precision UART Timer

(PUT) are primarily for reasons of upward compatibility from

earlier HPC family members The most flexible and accurate

on-chip clocking is provided by the third source the Baud

Rate Generator (BRG)

The Baud Rate Generator is controlled by the register pair

PSR and BAUD shown below

The Prescaler factor is selected by the upper 5 bits of the

PSR register (the PRESCALE field) in units of the CK2

clock from 1 to 16 in

step increments The lower 3 bits of

the PSR register in conjunction with the 8 bits of the baud

baud rate divisor ranging from 1 to 2048 in units of the

prescaled clock selected by the PRESCALE field

In Asynchronous Mode the resulting baud rate is

of the

clocking rate selected through the BRG circuit The maxi-

mum baud rate generated using the BRG is 625 kbaud

In the Synchronous Mode data is transmitted on the rising

edge and received on the falling edge of the external clock

Although the data is transmitted and received synchronous-

ly it is still contained within an asynchronous frame ie a

start bit parity bit (if selected) and stop bit(s) are still pres-

ent

TLDD10422 – 25

FIGURE 16 UART Block Diagram

TLDD10422 – 26

UART Baud Rate Generator (BRG) Registers PSR and BAUD

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