HPC-DEV-IBMC datasheet(17/30 Pages) NSC

17 / 30 page

UART Attention Mode

The HPC46400E UART features an Attention Mode of oper-

ation This mode of operation enables the HPC46400E to

be networked with other processors Typically in such envi-

ronments the messages consist of addresses and actual

data Addresses are specified by having the ninth bit in the

data frame set to 1 Data in the message is specified by

having the ninth bit in the data frame reset to 0

The UART monitors the communication stream looking for

addresses When the data word with the ninth bit set is

received the UART signals the HPC46400E with an inter-

rupt The processor then examines the content of the re-

ceiver buffer to decide whether it has been addressed and

whether to accept subsequent data

Programmable Serial Decoder

Interface

The programmable serial decoder interface allows the two

HDLC channels to be used with devices employing several

popular Time Division Multiplexing (TDM) serial protocols

for point-to-point and multipoint data exchanges These pro-

tocols combine the ‘B’ and ‘D’ channels onto common

pinsreceived data transmit data clock and Sync which

normally occurs at an 8 KHz rate and provides framing for

the particular protocol

The decoder uses the serial link clock and Sync signals to

generate internal enables for the ‘D’ and ‘B’ channels

thereby allowing the HDLC channels to access the appropri-

ate channel data from the multiplexed link

Additionally 64 kbits to 56 kbitss rate adaptation can be

done using the Serial Decoder generated enable signals B1

or B2 The rate adaption to 56 kbitss is accomplished by

using only the first 7 bits of each B channel time slot for

each TDM frame The transmitter will insert a ‘‘1’’ in the

eighth bit of each frame The receiver will only receive the

first seven data bits and skip the eighth bit See

Figure 17

65 kbit56 kbit Rate Adaption Timing Diagram

HDLC Channel Description

HDLCDMA Structure

HDLC 1

HDLC 2

HDLC1

HDLC2

Receive

Transmit

Receive

Transmit

DMAR1

DMAT1

DMAR2

DMAT2

GENERAL INFORMATION

Both HDLC channels on the HPC46400E are identical and

operate up to 465 Mbps When used in an ISDN Basic Rate

access application HDLC channel

1 has been designated

for use with the 16 kbps D-channel or either B channel and

HDLC

2 can be used with either of the 64 kbps B-chan-

nels If the ‘D’ and ‘B’ channels are present on a common

serial link the programmable serial decoder interface gen-

erates the necessary enable signals needed to access the

D and B channel data

There are two sources for the receive and transmit channel

enable signals They can be internally generated from the

serial decoder interface or they can be externally enabled

LAPD the Link Access Protocol for the D channel is derived

from the X25 packet switching LAPB protocol LAPD speci-

fies the procedure for a terminal to use the D channel for

the transfer of call control or user-data information The pro-

cedure is used in both point-to-point and point-to-multipoint

configurations On the HPC46400E the HDLC controller

contains user programmable features that allow for the effi-

cient processing of LAPD Information

HDLC Channel Pin Description

Each HDLC channel has the following pins associated with

HCK

HDLC Channel Clock Input Signal

Receive Serial Data Input Data latched on

the negative HCK edge

RENRHCK

HDLC Channel Receiver Enable InputRe-

ceiver Clock Input

TEN

HDLC Channel Transmitter Enable Input

Transmit Serial Data Output Data clocked

out on the positive HCK edge Data (not in-

cluding CRC) is sent LSB first TRI-STATE

when transmitter not enabled

CFLG1

Closing Flag output for Channel 1

HDLC Functional Description

TRANSMITTER DESCRIPTION

Data is transferred from external memory through the DMA

controller into the transmit buffer register from which it is

loaded into a 8-bit serial shift register The CRC is computed

and appended to the frame prior to the closing flag being

transmitted Data is output at the TX output pin If no further

transmit commands are given the transmitter sends out con-

tinous flags aborts or the idle pattern as selected by the

control register

An interrupt is generated when the DMA has transferred the

last byte from RAM to the HDLC channel for a particular

message or on a transmit error condition An associated

transmit status register will contain the status information

indicating the specific interrupt source

To support transmitting data packets at an ‘‘R’’ interface for

V120 in synchronous UI mode to support the use of the

HPC in test equipment or to support proprietary CRC algo-

rithms the transmitter has the option of preventing the trans-

mitting of the hardware generated CRC bytes

TRANSMITTER FEATURES

Interframe fill the transmitter can send either continuous

‘1’s or repeated flags or aborts between the closing flag of

one packet and the opening flag of the next When the CPU

commands the transmitter to open a new frame the inter-

frame fill is terminated immediately

Abort the abort sequence a zero followed by seven ones

will be immediately sent on command from the CPU or on

an underrun condition in the DMA

BitByte boundaries The message length between packet

headers may have any number of bits and is not confined to

an integral number of bytes Three bits in the control regis-

ter are used to indicate the number of valid bits in the last

byte These bits are loaded by the users software

RECEIVER DESCRIPTION

Data is input to the receiver on the RX pin The receive

clock can be externally input at either the HCK pin or the

RENRHCK pin

Incoming data is routed through one of several paths de-

pending on whether it is the flag data or CRC

Once the receiver is enabled it waits for the opening flag of

the incoming frame then starts the zero bit deletion ad-

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