PUSB3F96

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 3 — 29 September 2014

2 of 15

NXP Semiconductors

PUSB3F96

ESD protection for ultra high-speed interfaces

2.

Pinning information

3.

Ordering information

4.

Marking

5.

Limiting values

[1]

All pins to ground.

Table 1.

Pinning

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

CH1

channel 1 ESD protection

2

CH2

channel 2 ESD protection

3

GND

ground

4

CH3

channel 3 ESD protection

5

CH4

channel 4 ESD protection

6

n.c.

not connected

7

n.c.

not connected

8

GND

ground

9

n.c.

not connected

10

n.c.

not connected

Transparent top view

10

9876

12345

24

3, 8

018aaa001

1

5

Table 2.

Ordering information

Type number

Package

Name

Description

Version

PUSB3F96

DFN2510A-10

plastic extremely thin small outline package;

no leads; 10 terminals; body 1

 2.5  0.5 mm

SOT1176-1

Table 3.

Marking codes

Type number

Marking code

PUSB3F96

96

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

input voltage

0.5

+5.5

V

electrostatic discharge

voltage

IEC 61000-4-2, level 4

[1]

contact discharge

10

+10

kV

air discharge

15

+15

kV

ambient temperature

40

+85

C

storage temperature

55

+125

C