PUSB3F96

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 3 — 29 September 2014

3 of 15

NXP Semiconductors

PUSB3F96

ESD protection for ultra high-speed interfaces

6.

Characteristics

[1]

This parameter is guaranteed by design.

[2]

According to IEC 61000-4-5 (8/20

s current waveform).

[3]

100 ns Transmission Line Pulse (TLP); 50

; pulser at 80 ns.

Table 5.

Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

breakdown voltage

6

--V

reverse leakage current

--1

A

forward voltage

-0.7

-V

line capacitance

[1] -0.5

0.6

pF

C

line

line capacitance

difference

[1] -0.05

-pF

dynamic resistance

surge

[2]

positive transient

-

0.41

-



negative transient

-

0.26

-



TLP

[3]

positive transient

-

0.43

-



negative transient

-

0.28

-



clamping voltage

[2]

positive transient

-

4.6

-

V

[2]

negative transient

-

2.2

-

V