ST92195D datasheet(93/249 Pages) STMICROELECTRONICS

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ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE

TDSRAM (Cont’d)

RAM INTERFACE CONFIGURATION REGIS-

TER (CONFIG )

R252 - Read/Write

Reset Value: 0000 0110 (06h)

Bits 7:4 = Reserved, keep in reset state.

Bit 3 = DS:

Double Scan

When the DS bit is reset, the TDSRAM interface

and the CSYNC controller behave in 50Hz/60Hz

compatible mode. The acquisition storage is only

allowed up to the end of line 24. The EOFVBI inter-

rupt is generated at the beginning of line 25.

When the DS bit is set, the TDSRAM interface and

the CSYNC controller behave in 100/120Hz com-

patible mode. The EOFVBI interrupt is generated

at the beginning of deflection line 50.

Note: DS can be changed only when the TRI is off

(GEN = 0).

Bit 2 = AON:

Acquisition ON/OFF.

0: No acquisition storage allowed (acquisition slot

completely used for CPU access).

1: Acquisition storage enabled during the respec-

tive access slot.

Note: AON can be changed only when the TRI is

off (GEN = 0).

Bit 1 = DON:

Display ON/OFF.

0: No display reading allowed (display slot com-

pletely used for CPU access).

1: Display reading enabled during the respective

access slot.

Note: DON can be changed only when the TRI is

off (GEN = 0).

Bit 0 = GEN:

RAM Interface General Enable.

0: TRI off. Acquisition storage, display reading,

multi-byte transfer and CPU accesses are not

allowed. When GEN=0, the Automatic Wait Cy-

cle insertion, while trying to access the

TDSRAM, is disabled.

1: TRI on.

AON DON

GEN

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