STV8207 datasheet(41/149 Pages) STMICROELECTRONICS

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STV82x7

I²S Interface (In / Out)

Both standard and non-standard modes are available, see Figure 26.

6.2

I²S Output

A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a

converted input audio signal to an external device. In this case the I²S_DATA0 signal and all clock

signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the

serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency

(fs) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required

for the slave interface. Both standard and non-standard modes are available, see Figure 26.

Note:

The Input and Output modes for I²S are exclusive.

Table 6: I²S Frequency Configuration

I²S

(Max. Number of Channels)

fS Input (kHz)

fS Output (kHz)

after SRC

SRC Use

1 (I²S_DATA0)

32.0

x 4

1 (I²S_DATA0)

32.0

x 2

32.0

1 (I²S_DATA0)

11.025

44.1

x 4

1 (I²S_DATA0)

22.05

44.1

x 2

44.1

1 (I²S_DATA0)

48.0

x 4

1 (I²S_DATA0)

48.0

x 2

48.0

Figure 26: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode)

I²S_SCLK

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

1/fs

Lch

Rch

I²S_LR_CLK

(= 64fs)

I²S_DATAx

(standard mode)

I²S_DATAx

(non-standard mode)

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