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STM32MP151AAB3 数据表(PDF) 153 Page - STMicroelectronics |
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STM32MP151AAB3 数据表(HTML) 153 Page - STMicroelectronics |
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153 / 253 page  DS12500 Rev 3 153/253 STM32MP151A/D Electrical characteristics 232 fPLL_P_Q_R_ OUT PLL P,Q,R multiplier output clock - 3.125 - 800(2) MHz PLL P,Q,R clock duty cycle Even divisions (N multiple of 2) 45 50 55 % Odd divisions (N not multiple of 2) [100, (N+1)/ 2N] - 5 [100, (N+1)/ 2N] [100, (N+1)/ 2N] + 5 fVCO_OUT PLL VCO output - 400 - 800 MHz tLOCK PLL lock time Normal mode 15 50 150 µs Sigma-delta mode (CKIN ≥ 8 MHz) 25 65 170 ALOCK Lock accuracy (Ratio VCO frequency versus target frequency at lock) -- - ±2 % Jitter RMS cycle-to- cycle jitter fPLL_P_Q_R_OUT division = 25 to 100 Without Fractional mode VCO = 400 MHz - 80(3) - ±ps VCO = 600 MHz - 50(3) - VCO = 800 MHz - 45(3) - fPLL_P_Q_R_OUT division = 25 to 100 With Fractional mode VCO = 600 MHz - 65(3) - VCO = 800 MHz - 60(3) - RMS period jitter fPLL_P_Q_R_OUT division = 25 to 100 Without Fractional mode VCO = 400 MHz - 75(3) - ±ps VCO = 600 MHz - 38(3) - VCO = 800 MHz - 30(3) - fPLL_P_Q_R_OUT division = 25 to 100 With Fractional mode VCO = 600 MHz - 55(3) - VCO = 800 MHz - 50(3) - Long term jitter fPLL_P_Q_R_OUT division = 25 to 100 fPLL_IN = 8 MHz Without Fractional mode VCO = 400 MHz - 225(4) - ps VCO = 600 MHz - 150(4) - VCO = 800 MHz - 125(4) - fPLL_P_Q_R_OUT division = 25 to 100 fPLL_IN = 8 MHz With Fractional mode VCO = 400 MHz - 300(4) - VCO = 600 MHz - 200(4) - VCO = 800 MHz - 150(4) - IVDD_PLL PLL power consumption on VDD_PLL (Analog) VCO freq = 800 MHz - 600 610 µA VCO freq = 400 MHz - 320 350 Table 39. PLL3_800, PLL4_800 characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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