STM32MP151AAB3 datasheet(161/253 Pages) STMICROELECTRONICS

161 / 253 page

DS12500 Rev 3

161/253

STM32MP151A/D

Electrical characteristics

232

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT I/Os is shown in Figure 23.

Table 50. I/O static characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VIL(1)

I/O input low level voltage

1.71 V < VDD < 2.7 V

0.35 × VDD

2.7 V < VDD < 3.6 V

0.3 × VDD

1.71 V < VDD < 3.6 V

0.45 × VDD

+ 0.35

VIH(1)

I/O input high level voltage

1.71 V < VDD < 3.6 V

0.7 × VDD

VHYS(1)

TT_xx, FT_xxx and NRST I/O

input hysteresis

1.71 V < VDD < 3.6 V

0.1 ×

VDD

-mV

Ileak

FT_xx input leakage current(1)

0 < VIN ≤ Max(VDD)(6)

250

Max(VDD) < VIN ≤ 5.5 V

(6)(2)(3)

3500

FT_u, IO

0 < VIN ≤ Max(VDD)(6)

500

Max(VDD) < VIN ≤ 5.5 V

(6)(3)

5000(4)

TT_xx input leakage current

0 < VIN ≤ Max(VDD) (6)

100

RPU

Weak pull-up equivalent

resistor(5)

VIN=VSS

kΩ

RPD

Weak pull-down equivalent

resistor(5)

VIN=VDD(6)

CIO

I/O pin capacitance

1. Guaranteed by design.

2. All FT_xx IO except FT_uf, FT_u.

3. VIN must be less than Max(VDD) + 3.6 V.

4. To sustain a voltage higher than MIN(VDD, VDDA, VDD3V3_USBxxx) +0.3 V, the internal pull-up and pull-down resistors must

be disabled.

5. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

6. Max(VDD) is the maximum value of all the I/O supplies.

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