32KHz

OSC

DIVIDE BY

32768

1 Hz

READ / WRITE

BUFFER

TRANS FER

REGIS TERS

INTERFACE

CENTURIES

YEARS

MONTHS

DATE

DAY-OF-WEEK

HOURS

MINUTES

SECONDS

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

2

CLOCK COUNTERS ARE

ACCES S ED INDIRECTLY

THRU BUFFER/TRANS FER

REGIS TERS

FLAGS

NON-CLOCK

REGISTERS

CALIBRATION

WATCHDOG

NON-CLOCK REGIS TERS

ARE DIRECTLY ACCES S ED

DATA TRANS FERRED

OF S CL (ON WRITES )

ON WRITES, DATA TRANS FERRED

FROM BUFFERS TO COUNTERS

WHEN ADDRES S P OINTER

S TOP CONDITION IS RECEIVED

AT S TART OF READ, UDATES FROM COUNTERS

ARE HALTED AND P RES ENT TIME IS FROZEN

IN BUFFER/TRANS FER REGIS TERS.

Updates

During normal operation when the user is not accessing the device, the buffer/transfer registers are kept updated

with a copy of the RTC counters. At the start of an I²C read or write cycle, the updating is halted and the present

time is frozen in the buffer/transfer registers.

Reads of the clock registers

By halting the updates at the start of an I²C access, the user is ensured that all the data transferred out during a

read sequence comes from the same instant in time.

Write timing

When writing to the device, the data is shifted into the M41T62's I²C interface on the rising edge of the SCL

signal. As shown in Figure 17. Buffer/transfer registers, on the 8th clock cycle, the data is transferred from the I²C

block into whichever register is being pointed to by the address pointer (not shown).

Writes to the clock registers (addresses 0-7)

Data written to the clock registers (addresses 0-7) is held in the buffer registers until the address pointer

increments to 8, or an I²C stop condition occurs, at which time the data in the buffer/registers is simultaneously

copied into the counters, and then the clock is re-started.

M41T62, M41T64, M41T65

RTC registers

DS3840 - Rev 24

page 12/42