3.11

Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was

stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be

set to '1' any time the oscillator stops.

In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST)

should be written to a '1,' then immediately reset to '0.' This will restart the oscillator.

The following conditions can cause the OF bit to be set:

•

The first time power is applied (defaults to a '1' on power-up).

Note:

If the OF bit cannot be written to '0' four (4) seconds after the initial power-up, the STOP bit (ST) should be

written to a '1,' then immediately reset to '0.'

•

•

The ST bit is set to '1.'

•

External interference of the crystal

If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The IRQ output is

cleared by resetting the OFIE or OF bit to '0' (NOT by reading the flag register).

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4

seconds before attempting to reset the OF bit to '0.' If the trigger event occurs during a power-down condition, this

bit will be set correctly.

3.12

Initial power-on defaults

Upon application of power to the device, the register bits will initially power-on in the state indicated in

Table 9. Initial power-up values.

Condition

Device

ST

OF

OFIE

OUT

FT

AFE

SQWE

32KE

RS3-1

RS0

Watchdog

Initial power-

up(1)

M41T62

0

1

0

1

N/A

0

1

N/A

0

1

0

M41T64

0

1

N/A

N/A

N/A

N/A

0

1

0

1

0

M41T65

0

1

0

1

0

0

N/A

N/A

N/A

N/A

0

1. All other control bits power up in an undetermined state.

M41T62, M41T64, M41T65

Oscillator stop detection

DS3840 - Rev 24

page 21/42