PCF2129AT datasheet(38/86 Pages) PHILIPS

38 / 86 page

PCF2129

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Product data sheet

Rev. 7 — 19 December 2014

38 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF is set

logic 1

• When a minute or second interrupt occurs, the minute/second flag MSF is set logic 1

(see Section 8.12.1).

8.10.4 Pre-defined timers: second and minute interrupt

PCF2129 has two pre-defined timers which are used to generate an interrupt either once

per second or once per minute (see Section 8.12.1). The pulse generator for the minute or

second interrupt operates from an internal 64 Hz clock. It is independent of the watchdog

timer. Each of these timers can be enabled by the bits SI (second interrupt) and MI

(minute interrupt) in register Control_1.

8.10.5 Clearing flags

The flags MSF, AF, and TSFx can be cleared by command. To prevent one flag being

overwritten while clearing another, a logic AND is performed during the write access. A

flag is cleared by writing logic 0 while a flag is not cleared by writing logic 1. Writing logic 1

results in the flag value remaining unchanged.

Two examples are given for clearing the flags. Clearing a flag is made by a write

command:

• Bits labeled with - must be written with their previous values

• Bits labeled with T have to be written with logic 0

• WDTF is read only and has to be written with logic 0

Repeatedly rewriting these bits has no influence on the functional behavior.

Counter reached 1, WDTF is logic 1, and an interrupt is generated.

Fig 19. WD_CD set logic 1: watchdog activates an interrupt when timed out

Table 53.

Flag location in register Control_2

Bit

Control_2

MSF

WDTF

TSF2

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