AM29DL642G datasheet(12/54 Pages) AMD

12 / 54 page

Am29DL642G

June 10, 2005

PRELIMINARY

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Pro-

gram Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts VHH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

VHH from the WP#/ACC pin returns the device to nor-

mal operation. Note that VHH must not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 20. for related in-

formation.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 18 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. ICC6 and ICC7 in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# or CE2# and RESET# pins are both held at V

CC ±

0.3 V. (Note that this is a more restricted voltage range

than V

IH.) If CE# and RESET# are held at VIH, but not

within V

CC ± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (t

CE) for read ac-

cess when the device is in either of these standby

modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

CC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, CE2#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

CC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

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