MIMX8DX2AVOFZAC datasheet(64/151 Pages) NXP

部件名	MIMX8DX2AVOFZAC

功能描述	i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors

PDF	151 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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64 / 151 page

Electrical characteristics

i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 2, 03/2020

NXP Semiconductors

Below are the LPSPI interfaces and their respective chip selects:

4.10.1.1 LPSPI Master mode

Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0. Timing

parameters are valid for all modes using appropriate edge of the clock.

Figure 20. LPSPI Master mode

Table 59. LPSPI interfaces and chip selects

LPSPI interface

Chip select

Comment

60 MHz in Master mode and 40 MHz in

Slave mode

SPI0, SPI2, SPI2b, SPI3

SPI2 - default SPI2 balls

SPI2b - muxed behind audio balls

40 MHz in Master mode and 20 MHz in

Slave mode

SPI1, SPI1b, SPI2c

SPI1 - muxed behind SAI balls

SPI1b - muxed behind CSI balls

SP2c - muxed behind uSDHC1 balls

Table 60. LPSPI timings—Master mode at 60 MHz

Parameter

Min

Max

Unit

— SPIx_SCLK Cycle frequency

—

MHz

t1 SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

7.5

—

t2 SPIx_CSy pulse width

7.5

—

t3 SPIx_CSy Lead Time(1)

FCLK_PERIOD(2) x (PCSSCK

+ 1) / 2PRESCALE - 3

—ns

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