MIMX8DX2AVOFZAC datasheet(98/151 Pages) NXP

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Electrical characteristics

i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 2, 03/2020

NXP Semiconductors

4.10.13 Secure JTAG controller (SJC)

4.10.13.1 Internal pull-up/pull-down configuration

The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG

interface. External pull-ups and pull-downs are needed when this interface is routed to a connector.

Table 101. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode)

Parameter

Min

Max

Unit

—QSPIx[A/B]_SCLK Cycle frequency

—

200

MHz

QSPIx[A/B]_SCLK High or Low Time

2.25

—

QSPIx[A/B]_SSy_B pulse width

—

SCLK

QSPIx[A/B]_SSy_B Lead Time1

1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

(TCSS+0.5)/2

—

SCLK

QSPIx[A/B]_SSy_B Lag Time1

TCSH/2

—

SCLK

QSPIx[A/B]_DATAy output valid time

0.65

—

QSPIx[A/B]_DATAy output hold time

0.65

—

QSPIx[A/B]_DATAy Setup Skew

—

0.65

t10

QSPIx[A/B]_DATAy Hold Skew

—

0.65

Table 102. JTAG default configuration for internal pull-up/pull-down

Ball name

Internal pull setting1

1 PU = pull-up; PD = pull-down

Typical pull value

Unit

JTAG_TMS

JTAG_TCK

JTAG_TDI

TEST_MODE_SELECT

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