HMA82GS6AFR8N-TF datasheet(7/73 Pages) HYNIX

7 / 73 page

Rev. 1.4 / Sep.2017

A0 - A16

Input

Address Inputs: Provide the row address for ACTIVATE Commands and the column

address for Read/Write commands to select one location out of the memory array in the

respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 have

additional functions. See other rows. The address inputs also provide the op-code during

Mode Register Set commands.

A10 / AP

Input

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write

operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a

Precharge command to determine whether the Precharge applies to one bank (A10

LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected

by bank addresses.

A12 / BC_n

Input

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if

burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).

See command truth table for details.

RESET_n

CMOS

Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive

when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Input /

Output

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then

CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the

internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor

specific data sheets to determine which DQ is used.

DQS_t, DQS_c,

Input /

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. DDR4 SDRAMs support differential data strobe only and does not

support single-ended.

PARITY

Input

Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with

MR setting. Once it’s enabled via Register in MR5, then DSRAM calculates Parity with

ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity

should be maintained at the rising edge of the clock and at the same time with

command & address with CS_n LOW.

ALERT_n

Output

ALERT: It has multiple functions, such as CRC error flag or Command and Address Parity

error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for

the period time interval and goes back HIGH. If there is an error in Command Address

Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM

internal recovery transaction is complete.

During Connectivity Test mode, this pin functions as an input.

Use of this signal or not is dependent on the system.

SA0-SA1

Input Device address for the SPD.

RFU

Reserved for Future Use. No on DIMM electrical connection is present.

No Connect: No on DIMM electrical connection is present.

VDD1

Supply Power Supply: 1.2 V +/- 0.06 V

VSS

Supply Ground

VTT2

Supply Power Supply : 0.6V

Symbol

Type

Function

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