HMA82GS6AFR8N-TF datasheet(39/73 Pages) HYNIX

39 / 73 page

Rev. 1.4 / Sep.2017

Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure below.

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Single-ended Output Slew Rate Definition

Description: SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

NOTE:

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or

low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction

(i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction,

the regular maximum limit of 9 V/ns applies

Single-ended output slew rate definition

Description

Measured

Defined by

From

Single ended output slew rate for rising edge

VOL(AC)

VOH(AC)

[VOH(AC)-VOL(AC)] /

Delta TRse

Single ended output slew rate for falling edge

VOH(AC)

VOL(AC)

[VOH(AC)-VOL(AC)] /

Delta TFse

Single-ended output slew rate

Parameter

Symbol

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Single ended output slew rate

SRQse

494

94949

494949

V/ns

VOH(AC)

VOL(AC)

delta

TRse

delta

TFse

HMA82GS6AFR8N-TF 数据表(PDF) 39 Page - Hynix Semiconductor

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