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WM8742GEDS/RV 数据表(PDF) 46 Page - Cirrus Logic

部件名 WM8742GEDS/RV
功能描述  24-bit 192 kHz DAC with Advanced Digital Filtering
PDF  66 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8742GEDS/RV 数据表(HTML) 46 Page - Cirrus Logic

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WM8742
46
Rev 4.4
REGISTER
ADDRESS
BITS
NAME
DEFAULT
DESCRIPTION
R0
DACLLSB
Attenuation
00h
[4:0]
LAT[4:0]
00 (0dB)
LSBs of attenuation data for left channel in 0.125dB steps. See Table
25 for details.
5
UPDATE
0
Attenuation data load control for left channel.
0 =
Store LAT[4:0] value but don’t update
1 = Store LAT[4:0] and update attenuation on registers 0-3
Table 53 R0 DACL LSB Attenuation Control Register
REGISTER
ADDRESS
BITS
NAME
DEFAULT
DESCRIPTION
R1
DACLMSB
Attenuation
01h
[4:0]
LAT[9:5]
00 (0dB)
MSBs of attenuation data for left channel in 4dB steps. See Table 25
for details.
5
UPDATE
0
Attenuation data load control for left channel.
0 =
Store LAT[9:5] value but don’t update
1 = Store LAT[9:5] and update attenuation on registers 0-3
Table 54 R1 DACL MSB Attenuation Control Register
REGISTER
ADDRESS
BITS
NAME
DEFAULT
DESCRIPTION
R2
DACRLSB
Attenuation
02h
[4:0]
RAT[4:0]
00 (0dB)
LSBs of attenuation data for right channel in 0.125dB steps. See
Table 25 for details.
5
UPDATE
0
Attenuation data load control for right channel.
0 =
Store RAT[4:0] value but don’t update
1 = Store RAT[4:0] and update attenuation on registers 0-3
Table 55 R2 DACR LSB Attenuation Control Register
REGISTER
ADDRESS
BITS
NAME
DEFAULT
DESCRIPTION
R3
DACRMSB
Attenuation
03h
[4:0]
RAT[9:5]
00 (0dB)
MSBs of attenuation data for right channel in 4dB step. See Table 25
for details.
5
UPDATE
0
Attenuation data load control for right channel.
0 =
Store RAT[9:5] value but don’t update
1 = Store RAT[9:5] and update attenuation on registers 0-3
Table 56 R3 DACR MSB Attenuation Control Register



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