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WM8742GEDS/RV 数据表(PDF) 12 Page - Cirrus Logic |
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WM8742GEDS/RV 数据表(HTML) 12 Page - Cirrus Logic |
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12 / 66 page ![]() WM8742 12 Rev 4.4 PCM DIGITAL AUDIO INTERFACE TIMING BCLK LRCLK t BCH t BCL t BCY DIN t LRSU t DS t LRH t DH V IH V IL V IH V IL V IH V IL Figure 2 Digital Audio Data Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 40 ns BCLK pulse width high tBCH 16 ns BCLK pulse width low tBCL 16 ns LRCLK set-up time to BCLK rising edge tLRSU 8 ns LRCLK hold time from BCLK rising edge tLRH 8 ns DIN set-up time to BCLK rising edge tDS 8 ns DIN hold time from BCLK rising edge tDH 8 ns Table 2 Digital Audio Interface Timing Requirements |
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