IS25LP032D-RGLA3 datasheet(85/118 Pages) ISSI

85 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

FAST READ DTR MODE OPERATION IN QPI MODE (FRDTR, 0Dh)

The FRDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two clocks

are required, while the FRDTR instruction requires that the byte-long instruction code is shifted into the device only

via IO0 line in eight clocks. In addition, subsequent address and data out are shifted in/out via all four IO lines unlike

the FRDTR instruction. Eventually this operation is same as the FRQDTR in QPI mode, but the only different thing

is that AX mode is not available in the FRDTR operation in QPI mode.

The sequence of issuing FRDTR instruction in QPI mode is: CE# goes low  Sending FRDTR instruction (4-bit

per clock)  24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  6 dummy clocks (configurable,

default is 6 clocks)  Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  End FRDTR operation in QPI

mode by driving CE# high at any time during data out.

If the FRDTR instruction in QPI mode is issued while a Program/Erase/Write Status Register cycle is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

Figure 8.64 FRDTR Sequence In QPI Mode

Instruction

= 0Dh

CE #

SCK

3-byte Address

Mode 3

Mode 0

20 16 12

5 1

21 17 13

4 0

IO0

IO1

22 18 14

23 19 15

8 4

9 5

10 6

11 7

6 Dummy Cycles

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

...

Notes:

1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

2. Sufficient dummy cycles are required to avoid I/O contention.

IS25LP032D-RGLA3 数据表(PDF) 85 Page - Integrated Silicon Solution, Inc

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