IS25LP032D-RGLA3 datasheet(67/118 Pages) ISSI

67 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.24 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h)

Set Read Parameter Bits

This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three bits

(P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the SRPNV

and SRPV operation instruction are used. Details regarding burst length and dummy cycles can be found in Table

6.9, Table 6.10, and Table 6.11. HOLD#/RESET# pin selection (P7) bit in the Read Register can be set with the

SRPNV and SRPV operation as well, in order to select HOLD#/RESET# pin as RESET# or HOLD#.

For the device with dedicated RESET# pin (or ball), RESET# pin (or ball) will be a separate pin (or ball) and it is

independent of the P7 bit setting in Read Register

SRPNV is used to set the non-volatile Read register, while SRPV is used to set the volatile Read register.

Note: When SRPNV is executed, the volatile Read Register is set as well as the non-volatile Read Register.

Figure 8.40 Set Read Parameters Sequence In SPI Mode

Instruction = 65h or C0h/63h

CE #

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.41 Set Read Parameters Sequence In QPI Mode

65h or

C0h/63h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

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