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IS25LP064A-RBLA2 数据表(PDF) 15 Page - Integrated Silicon Solution, Inc |
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IS25LP064A-RBLA2 数据表(HTML) 15 Page - Integrated Silicon Solution, Inc |
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15 / 99 page  IS25LP064A/032A Integrated Silicon Solution, Inc.- www.issi.com 15 Rev. A 11/06/2015 6. REGISTERS The IS25LP064A/032A has three sets of Registers: Status, Function and Read. 6.1 STATUS REGISTER Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2. Table 6.1 Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD QE BP3 BP2 BP1 BP0 WEL WIP Default 0 0 0 0 0 0 0 0 Table 6.2 Status Register Bit Definition Bit Name Definition Read- /Write Type Bit 0 WIP Write In Progress Bit: "0" indicates the device is ready(default) "1" indicates a write cycle is in progress and the device is busy R Volatile Bit 1 WEL Write Enable Latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled R/W 1 Volatile Bit 2 BP0 Block Protection Bit: (See Table 6.4 for details) "0" indicates the specific blocks are not write-protected (default) "1" indicates the specific blocks are write-protected R/W Non-Volatile Bit 3 BP1 Bit 4 BP2 Bit 5 BP3 Bit 6 QE Quad Enable bit: “0” indicates the Quad output function disable (default) “1” indicates the Quad output function enable R/W Non-Volatile Bit 7 SRWD Status Register Write Disable: (See Table 7.1 for details) "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected R/W Non-Volatile Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command. The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0” at factory. The Status Register can be read by the Read Status Register (RDSR). The function of Status Register bits are described as follows: WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. When the WIP bit is “0”, the device is ready for write Status Register, program or erase operation. When the WIP bit is “1”, the device is busy. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL is “0”, the write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When the WEL bit is “1”, the write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write register, program and erase instruction except for Set Read Register must be preceded by a WREN instruction. The WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of any write operation. |
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