JS28F128P30T85 datasheet(21/102 Pages) INTEL

21 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

VCCQ

Power

Output Power Supply: Output-driver source voltage.

VSS

Power

Ground: Connect to system ground. Do not float any VSS connection.

RFU

—

Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These

should be treated in the same way as a Do Not Use (DU) signal.

—

Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

—

No Connect: No internal connection; can be driven or floated.

Table 3.

TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)

Symbol

Type

Name and Function

Table 4.

QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

A[MAX:0]

Input

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0];

512-Mbit: A[24:0].

See Table 6 on page 22, Figure 11 on page 23, and Figure 12 on page 23 for 512-Mbit and 1-Gbit

addressing.

DQ[15:0]

Input/

Output

DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls

float when the CE# or OE# are deasserted. Data is internally latched during writes.

ADV#

Input

ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on

the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

In asynchronous mode, the address is latched when ADV# going high or continuously flows through

if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

F1-CE#

F2-CE#

Input

FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When

deasserted, the associated flash die is deselected, power is reduced to standby levels, data and

WAIT outputs are placed in high-Z state.

See Table 6 on page 22 for CE# assignment definitions.

WARNING: All chip enables must be high when device is not in use.

CLK

Input

CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

F1-OE#

F2-OE#

Input

OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high places the data outputs and WAIT in High-Z.

F1-OE# and F2-OE# should be tied together for all densities.

RST#

Input

RESET: Active low input. RST# resets internal automation and inhibits write operations. This

provides data protection during power transitions. RST# high enables normal operation. Exit from

reset places the device in asynchronous read array mode.

WAIT

Output

WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration

VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.

•

In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and

valid data when deasserted.

•

In asynchronous page mode, and all write modes, WAIT is deasserted.

WE#

Input

WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched

on the rising edge of WE#.

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