JS28F128P30T85 datasheet(39/102 Pages) INTEL

39 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

Note:

WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to

assert either during or one data cycle before valid data.

This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is

terminated by CE# deassertion after the first word in the burst.

Figure 18.

Asynchronous Page-Mode Read Timing

R108

R17

R15

R10

R106

R101

R105

A[Max:2] [A]

A[1:0]

ADV#

CE# [E]

OE# [G]

WAIT [T]

DATA [D/Q]

Figure 19.

Synchronous Single-Word Array or Non-array Read Timing

R312

R305

R304

R17

R307

R15

R303

R102

R104

R106

R101

R104

R105

R306

R301

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

JS28F128P30T85 数据表(PDF) 39 Page - Intel Corporation

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