7

Layout recommendations

The integrates the power stage; in order to improve the thermal dissipation, the exposed pad must be connected

to the ground plane on the bottom layer using multiple vias equally spaced. This ground plane acts as a heatsink,

for this reason it should be as wide as possible.

The voltage supply VS must be stabilized and filtered with a ceramic bypass capacitor, typically 330nF. It must be

placed on the same side and as close as possible to VS pin in order to reject high frequency noise components

on the supply. A bulk capacitor could also be required (typically a 33 μF). The connection between the power

supply connector and the VS pins must be as short as possible using wide traces.

In order to ensure the best ground connection between the and the other components, a GND plane surrounding

the device is recommended.

A capacitor between REF pins and ground should be positioned as near as possible to the device in order to filter

the noise and stabilize the reference voltage.

Several vias should be positioned as near as possible each sense resistor connecting them to the ground plane

on the bottom layer. In this way, both the GND planes provide a path for the current flowing into the power stage.

The path between the ground of the shunt resistors and the ceramic bypass capacitor of the device is critical; for

this reason it must be as short as possible minimizing parasitic inductances that can cause voltage spikes on

SENSE and OUT pins.

The OUT pins and the VS nets can be routed using the bottom layer, it is recommended to use two vias for output

connections.

VREF capacitor

for noise filtering

placed close to VREF

leads

STSPIN830

Ground plane:

connects all

the grounds on

the TOP layer

to reduce

parasitic effects

Vias on exposed pad

to improve thermal dissipation

Shunt resistor close to

respective SENSE and

SNS leads

Ceramic bypass

capacitor close to

VS leads

Several vias

to connect

the shunt ground

with the bottom

ground plane

Several vias

to connect

the shunt ground

with the bottom

ground plane

OUT tracks

vias

OUT tracks

vias

AM040390

In case of single shunt configuration take special care for the SENSE and SNS pins connection.

As suggested in the Figure 15. PCB layout example with single shunt (top layer) and Figure 16. PCB layout

example with single shunt (bottom layer), the shunt resistor can be placed in the top layer close to SENSEU and

SNS pins with a wide copper area and vias. The connection with other sense pins (SENSEV and SENSEW) can

be routed in the bottom layer taking care to maximize the track area and add more vias near to the pins.

STSPIN830

Layout recommendations

DS12584 - Rev 2

page 18/27