List of figures

Figure 1.

STSPIN830 block diagram ............................................................ 2

Figure 2.

Pin connection (top view) ............................................................. 7

Figure 3.

UVLO protection management ......................................................... 9

Figure 4.

PWM current limit sequence example ................................................... 11

Figure 5.

OFF time regulation circuit ........................................................... 11

Figure 6.

OFF time vs ROFF value ............................................................ 12

Figure 7.

Overcurrent and short-circuit protections management ....................................... 13

Figure 8.

Disable time versus REN and CEN values (VDD = 3.3 V)...................................... 14

Figure 9.

Overcurrent threshold versus temperature (normalized at 25 °C)................................. 14

Figure 10.

Thermal shutdown management ....................................................... 15

Figure 11.

ESD protection strategy ............................................................. 15

Figure 12.

Typical application schematic with single shunt ............................................. 16

Figure 13.

Typical application schematic with triple shunt ............................................. 17

Figure 14.

PCB layout example with triple shunt (top layer) ............................................ 18

Figure 15.

PCB layout example with single shunt (top layer) ........................................... 19

Figure 16.

PCB layout example with single shunt (bottom layer) ......................................... 19

Figure 17.

TFQFPN 4 x 4 x 1.05 - 24L package outline ............................................... 20

Figure 18.

TFQFPN 4 x 4 x 1.05 - 24L suggested footprint ............................................ 21

STSPIN830

List of figures

DS12584 - Rev 2

page 26/27