MCP47CMB02 datasheet(22/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 22

 2018-2019 Microchip Technology Inc.

Timing Notes:

Not tested. This parameter is ensured by characterization.

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.

The transition of the LAT signal, between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge

(Spec 95) of the SCL signal, is indeterminate whether the change in VOUT is delayed or not.

Use Cb in pF for the calculations.

A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does

not unintentionally create a Start or Stop condition.

A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the

requirement, tSU:DAT  250 ns, must then be met. This will automatically be the case if the device does not stretch

the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output

the next data bit to the SDA line, TR max.+ tSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C

bus specification) before the SCL line is released.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Ensured by the TAA 3.4 MHz specification test.

The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

10. Not tested. This parameter is ensured by design.

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