MCP47CMB02 datasheet(61/124 Pages) MICROCHIP

61 / 124 page

 2018-2019 Microchip Technology Inc.

DS20006089B-page 61

MCP47CXBXX

5.2

Voltage Reference Selection

The resistor ladder has up to four sources for the refer-

ence voltage. The selection of the voltage reference

source is specified with the Volatile VREF1:VREF0

Configuration bits (see Register 4-2). The selected

voltage source is connected to the VRL node (see

Figure 5-3 and Figure 5-4).

The four voltage source options for the Resistor Ladder

are:

VDD pin voltage.

Internal Band Gap Voltage Reference (VBG).

VREF pin voltage – unbuffered.

VREF pin voltage – internally buffered.

On a POR/BOR event, the default configuration state or

the value written in the Nonvolatile register is latched into

the Volatile VREF1:VREF0 Configuration bits.

If the VREF pin is used with an external voltage source,

then the user must select between Buffered or

Unbuffered mode.

FIGURE 5-3:

Resistor Ladder Reference

Voltage Selection Block Diagram.

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

5.2.1

USING VDD AS VREF

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the resistor ladder. The

VDD voltage is internally connected to the resistor

ladder.

5.2.2

USING AN EXTERNAL VREF

SOURCE IN UNBUFFERED MODE

In this case, the VREF pin voltage may vary from VSS to

VDD. The voltage source should have a low output

impedance. If the voltage source has a high output

impedance, then the voltage on the VREF pin could be

lower than expected. The resistor ladder has a typical

impedance of 71 k

 and a typical capacitance of 29 pF.

If a single VREF pin is supplying multiple DACs, the

VREF pin source must have adequate current capability

to support the number of DACs. It must be assumed

that the Resistor Ladder Resistance (RRL) of each DAC

is at the minimum specified resistance and these

resistances are in parallel.

If the VREF pin is tied to the VDD voltage, selecting

the VDD Reference mode (VREF1:VREF0 = 00) is

recommended.

VRL

VDD

Buffer

VREF1:VREF0

VREF

Band Gap

Note 1: The Band Gap Voltage (VBG) is 1.214V

typical. The band gap output goes

through the buffer with a 2x gain to

create the VRL voltage. See Table 5-1

for additional information on the

band gap circuit.

VDD

VRL

Band Gap(1)

(1.214V typical)

VDD

VREF

PD1:PD0 and

VREF1:VREF0

PD1:PD0 and

VREF1:VREF0

PD1:PD0 and

VREF1:VREF0

MCP47CMB02 数据表(PDF) 61 Page - Microchip Technology

MCP47CMB02 数据表(HTML) 61 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

MCP47CMB02 数据表(PDF) 61 Page - Microchip Technology

MCP47CMB02 数据表(HTML) 61 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载