MCP47CMB02 datasheet(80/124 Pages) MICROCHIP

80 / 124 page

MCP47CXBXX

DS20006089B-page 80

 2018-2019 Microchip Technology Inc.

FIGURE 7-5:

Read Command – Last Memory Address Accessed.

Note 1:

The Master device is responsible for the A/A signal. If an A signal occurs, the MCP47CXBXX will

abort this transfer and release the bus.

This Acknowledge bit is generated by the Master device.

This command sequence does not need to terminate (using the Stop bit) and the read command can

be repeated (see Section 7.6.2 “Continuous Reads”).

The Master device will Not Acknowledge and the MCP47CXBXX will release the bus so the Master

device can generate a Stop or Repeated Start condition.

The MCP47CXBXX retains the last received “Device Memory Address”.

The non-data bits of the Read Data Word will be output as ‘0’s:

for 12-bit devices, bits D15:D12 are ‘0’s

for 10-bit devices, bits D15:D10 are ‘0’s

for 8-bit devices, bits D15:D08 are ‘0’s

If the last device address written (via the read or write command) is invalid for a read, then the read

last memory address command will NACK due to the invalid device memory address.

I2C ACK Bit(1)

I2C Start Bit

I2C Slave Address

I2C Stop Bit(3)

nn Data (read from memory)

Control Byte

Legend:

Data Read MSB

Data Read LSB

A I2C ACK Bit(2)

I2C NACK Bit(4)

1 I2C Read Bit

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